Retention of data during stand-by mode

ABSTRACT

An embodiment of the present disclosure refers to retention of data in a storage array in a stand-by mode. A storage device comprises one or more storage array nodes, and a Rail to Rail voltage adjustor operatively coupled to the storage array nodes. The Rail to Rail voltage adjustor is configured to selectively alter the voltage provided at each said storage array node during stand-by mode. The storage device may further comprise a storage array operatively coupled to said Rail to Rail voltage adjustor and a Rail to Rail voltage monitor operatively coupled to said storage array nodes and configured to control said Rail to Rail voltage adjustor to provide sufficient voltage to retain data during stand-by mode.

PRIORITY CLAIM

The present application is a Divisional of copending U.S. patentapplication Ser. No. 12/817,086, filed Jun. 16, 2010, which applicationclaims the benefit of the Indian Patent Application No. 1249/Del/2009,filed Jun. 17, 2009, which application is incorporated herein byreference.

TECHNICAL FIELD

An embodiment of the present disclosure relates to retention of data instorage arrays and more particularly, but not limited to, retention ofdata in a storage array during stand-by mode.

BACKGROUND

The following description of the background art may include insights,discoveries, understandings or disclosures, or associations togetherwith disclosures not known to the relevant art but provided by thedisclosure. Some such contributions of the disclosure may bespecifically pointed out below, whereas other such contributions will beapparent from their context.

The terms ‘stand by’ and ‘sleep mode’ as well as ‘memory’, ‘data storagearray’ and ‘storage array’ have been used interchangeably throughout thepresent disclosure.

Memories comprise several memory columns comprising memory cells forstorage and access of data. However, each column conducts a leakagecurrent which increases with increase in the supply voltage of thememory. The larger the memory size, the more leakage current and powerconsumption by the memory.

To reduce leakage in memory devices comprising said memory, stand bymode is utilized wherein reduced voltages are applied during inactivephases of a circuit such as during outside read and write phases.However, when Rail to Rail voltage across a memory decreases below a setthreshold voltage, the circuit may switch states in response to thedisturbances. The difference between a higher voltage being applied atone terminal of a memory core and a lower voltage being applied at thesecond terminal of the memory terminal is referred to as Rail to Rail(RTR) voltage.

In view of the above, data retention power gating is used such that whenthe memory goes into the stand-by mode; sufficient voltage is presentacross the memory to retain the data. However, there are cases when thesupply voltage is very low and data retention with sufficient noisemargin may be difficult to achieve.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments and features of the present disclosure will be explained inthe following non-limiting description, taken in conjunction with theaccompanying drawings, wherein

FIG. 1 illustrates a graphical representation of an embodiment of thepresent disclosure.

FIGS. 2A and 2B illustrate block diagrams representation of a storagedevice capable of retaining data in stand-by mode in accordance with anembodiment of the present disclosure.

FIG. 3 illustrates an elemental representation of a storage devicecapable of retaining data during stand-by mode in accordance with anembodiment of the present disclosure.

FIG. 4 illustrates a low leakage tracking block in accordance with anembodiment of the present disclosure.

FIG. 5 illustrates a level sensing block in accordance with anembodiment of the present disclosure.

FIG. 6 illustrates a flow diagram representation of a method forretention of data in storage arrays during stand-by mode in accordancewith an embodiment of the present disclosure.

FIG. 7 illustrates a graphical representation of generation of controlsignal by the Rail to Rail (RTR) voltage monitor in accordance with anembodiment of the present disclosure.

FIG. 8 illustrates a graphical representation of leakage variation withrespect to current in accordance with an embodiment of the presentdisclosure.

DETAILED DESCRIPTION

Embodiments of the present disclosure will now be described in detailwith reference to the accompanying drawings. However, the presentdisclosure is not limited to these embodiments. The present disclosurecan be modified in various forms. Thus, the embodiments of the presentdisclosure are only provided to explain more clearly the presentdisclosure to the ordinarily skilled in the art of the presentdisclosure. In the accompanying drawings, like reference numerals areused to indicate like components.

An embodiment of the present disclosure describes a storage devicecapable of retaining data in a stand-by mode. The storage devicecomprises one or more storage array nodes, a Rail to Rail (RTR) voltageadjustor, a storage array operatively coupled to said RTR voltageadjustor and a RTR voltage monitor. The RTR voltage adjustor isoperatively coupled to one or more supply voltage nodes and isconfigured to selectively alter the voltage provided at each saidstorage array node during the stand-by mode. This is implemented bycontrolling the RTR voltage adjustor by the RTR voltage monitor suchthat sufficient voltage is provided across the storage array to retaindata during stand-by mode. An example of an embodiment of the presentdisclosure comprises two supply voltage nodes providing voltage V_(DD)and ground V_(GND) to two storage array nodes of said storage arraywherein the storage array comprises an array of memory cell rows andcolumns operable in a stand-by mode.

FIG. 1 illustrates a graphical representation of an embodiment of thepresent disclosure. As is clear from the graph plotted between the Railto Rail (RTR) voltage and time, the RTR voltage is monitored, and inaccordance with set supply voltages V1, V2, and V3 (where V1<V2<V3),stand-by mode is applied. V1 is the minimum supply voltage required toretain data in a storage array. If at a given point of time, theoperating band of the RTR voltage lies between supply voltages V1 and V2(range of V1-V2 is referred to as an operating band of low voltages),there is no sleep i.e., stand-by mode applied at header and footer ofsaid storage device as the voltage is sufficient enough to retain dataand also leakage encountered is minimal. Thus, exhibiting that even atvery low voltages the storage device is capable of retaining data.However, if the operating band of the RTR voltage falls between supplyvoltages V2 and V3 (range of V2-V3 is referred to as an operating bandof intermediate voltages), sleep is applied to either the header orfooter of the storage device However, should the operating band of theRTR voltage be greater than supply voltage V3 (range of >V3 is referredto as an operating band of high voltages), sleep is applied to both theheader and footer of the storage device. Thus, various embodiments ofthe present disclosure follow a dynamic mechanism of applying stand-bymode in a storage device such that an effective retention noise marginis maintained whenever the RTR voltage is selectively altered.

FIG. 2A illustrates a block diagram representation of a storage devicecapable of retaining data in stand-by mode in accordance with anembodiment of the present disclosure. The storage device comprises oneor more storage array nodes 201, a Rail to Rail (RTR) voltage adjustor202 operatively coupled to a storage array 203 and a Rail to Rail (RTR)voltage monitor 204 operatively coupled to supply voltage node 211 andconfigured to control said RTR voltage adjustor to provide sufficientvoltage to retain data in the storage array during stand-by mode. Thestorage array node 201 is operatively coupled to the RTR voltageadjustor 202, which comprises at least one switched voltage reductionelements such as controllable diodes.

During a stand-by mode, the RTR voltage adjustor 202 selectively altersthe voltage provided at each said storage array node 201 on receivingcontrol by the RTR voltage monitor 204. The monitor 204 tracks the RTRvoltage along the supply voltage and in accordance with the graphicalrepresentation illustrated in FIG. 1 sends a control signal to the RTRvoltage adjustor 202 to configure either header or footer or both instand-by mode. Accordingly RTR voltage at each storage array node 201 isaltered depending on the supply voltage provided and leakage is reducedand data is retained. Further, FIG. 2A shows a controller disposed on aseparate integrated circuit die coupled to a first integrated circuitdie upon which the storage device is disposed

FIG. 2B also illustrates a block diagram representation of a storagedevice capable of retaining data in stand-by mode in accordance with anembodiment of the present disclosure. In this embodiment, the controllerand the storage device are disposed on a single integrated circuit die.

FIG. 3 illustrates an elemental representation of a storage devicecapable of retaining data during stand-by mode in accordance with anembodiment of the present disclosure. Transistors M31 and M34 and memorycore form the data storage array 303 wherein said memory core is enabledthrough ENB and EN. The data storage array 303 receives supply voltagesat V_(DD) and V_(GND) at two supply voltage nodes 311(a), 311(b) asshown in the figure.

Transistors M32 302(a), M33 302(b), M35 302(c) and M36 302(d) form theRTR voltage adjustor wherein 302(a) and 302(b) form a header of thestorage device while 302(c) and 302(d) form a footer of the storagedevice. 304 indicates the RTR voltage monitor where according to anembodiment of the present disclosure, the monitor is a low leakagetracking block. The low leakage tracking block 304 tracks and monitorsthe RTR voltage and accordingly produces control signals 304(a) and304(b) to control the header 302(a), 302(b) and footer 302(c), 302(d) ofthe storage device. This control then selectively alters the voltageacross storage array nodes 301(a) and 301(b).

In accordance with an embodiment as well as referring to theillustration of FIG. 1, when the RTR voltage at storage array node301(a), 301(b) lies between supply voltages V1 and V2, no sleep isapplied to the storage device as the voltage is sufficient to retaindata. That is, neither of the signals 304(a) or 304(b) are asserted bythe voltage monitor 304, and no sleep mode is activated. However, whenthe RTR voltage at storage array node 301(a), 301(b) lies between supplyvoltages V2 and V3, sleep is applied to the header 302(a), 302(b), byasserting the signal 304(a). That is, sleep mode is activated for theheader by turning off the transistor 302(b). However, if the RTR voltageat the node exceeds supply voltage V3, sleep is applied to the header302(a), 302(b) as well as the footer 302(c), 302(d) of the storagedevice. That is, both of the signals 304(a) and 304(b) are asserted,thereby activating sleep mode by turning off the respective transistors402(b) and 402(d). This ensures that increase in leakage current due toincrease in supply voltage is kept in check and that the data isretained while maintaining effective retention noise margin. If the RTRvoltage at the storage array falls below the thresholds V3 and V2,respectively, then the signals 304(b) and 304(a) are deasserted,respectively. Such a deassertation of one or both of these signals304(b) and 304(a) results in a lowering of the overall impedance betweenthe rails of the RTR voltage as the application of non-sleep modeprovides an additional current path through one of the respectiveswitches 302(b) or 302(d).

To reiterate, as the RTR voltage crosses the first threshold V2, theoverall impedance between the rails increases because the transistor402(b) is turned off. Similarly, as the RTR voltage crosses the secondvoltage threshold V3, the overall impedance between the rails increasesagain because the footer transistor is turned off. When the RTR voltagebegins to fall, the overall impedance between the rails decreases at therespective steps of the voltage thresholds corresponding to V3 and V2respectively as the transistors 402(d) and 402(b) are once again turnedback on by the deassertation of the control signal 404.

FIG. 4 describes yet another embodiment of the present disclosurewherein a low leakage tracking block is illustrated. The currentembodiment refers to a scenario when the RTR voltage falls between therange of supply voltages V2 and V3. Accordingly, in the currentembodiment the header is configured to the sleep mode while the footerremains active.

The low leakage tracking block comprises a reference column 405 the RTRvoltage (e.g., the voltage between 411(a) and 411(b) at its terminalsthrough diodes M22 and M21 coupled to nodes 411(a) and 411(b). Thereference column 405 comprises more memory cells N′ per column than thecolumns in the storage array and is approximated by:

N′=kN

Where N=number of memory cells in normal column in the storage array

-   -   N′=number of memory cells in reference column    -   k=multiplying factor

The low leakage tracking block also comprises a level sensing block 406operatively coupled to the reference column 405 receiving V_(refGND)from node 407. The voltage V_(refGND) at node 407 is dependent onleakage of the reference column 405, thus making the control signal 404dependent on leakage. Hence, configuration of the RTR voltage adjustoris dynamically controlled. In an embodiment, as the RTR voltage iswithin the range of supply voltages V2 and V3, the header of the RTRvoltage adjustor is configured to the stand-by mode by the controlsignal 404. That is, the transistor M33 is turned off to increase theimpedance, and thus increase the voltage drop, between the nodes 411(a)and 401(a), this reduces the voltage across the array 403, and thushelps maintain the leakage within the array 403 to an acceptable level.Similarly, as the RTR voltage falls below V2, the header of the RTRvoltage adjustor is configured to no longer be in the stand-by mode bythe control signal 404. That is, the transistor M33 is turned on todecrease the impedance, and thus decrease the voltage drop, between thenodes 411 (a) and 401 (a), this increases the voltage across the array403. A footer circuit between the nodes 401(b) and 411(b) may operate ina similar manner.

FIG. 5 describes a level sensing block in accordance with an embodimentof the present disclosure. The level sensing block comprises a noninverting buffer with hysteresis i.e., a Schmitt trigger. The buffercomprises a plurality of transistors 506(a), 506(b), 506(c), 506(d),506(e), 506(f) and 506(g) configured as inverters wherein switch pointof inverters 506(a)/506(b), 506(d)/506(e) and 506(f)/506(g) is set by aswitch point ratio factor multiplied by V_(DD). Assuming that Node A isinitially logic “1” as V_(DD) begins to rise, Node B will be equivalentto logic “0”, Node C to that of logic “1” and Node D shall be equivalentto logic “0”. Transistor 506(c) is such a case shall be OFF. However, asV_(DD) rises above a certain threshold voltage, the switch point risesto a voltage above voltage at Node A. Therefore, Node A appears as logic“0”, Node B appears as logic “1”, Node C as logic “0” and Node D aslogic “1” while transistor 506(c) is turned ON.

The logic signal at Node D in turn controls and triggers the header andfooter of the RTR voltage adjustor of the storage device and is referredto as the control signal 504. Transistor 506(c) of the level sensingblock adds hysteresis to the buffer so that the switch point of506(a)/506(b) will be higher and V_(DD) will have to drop lower beforereset becomes active again.

Referring to the embodiment described in FIG. 4 of the presentdisclosure, it is clear that as V_(DD) rises above a set supply voltage,i.e., V2, the logic at Node D becomes “1” and hence, the header movesinto the sleep mode by turning off transistor M33, thereby ensuring thatleakage is maintained relatively low, retention noise margin ismaintained, and data is retained. FIG. 4 is specific to the case whereinV2<V_(DD)<V3.

However, in another embodiment of the present disclosure, whenV_(DD)>V3, two control signals are generated by an embodiment of amechanism similar to that illustrated in FIG. 5 wherein the signalsconfigure both header and footer in stand-by mode. Because the footermay include NMOS transistors, the signal at node 504 may be invertedbefore being provided to the footer.

An embodiment of a method to reduce leakage in a storage array in astand-by mode is described in FIG. 6. The method is illustrated as acollection of blocks in a logical flow graph, which represents asequence of operations that can be implemented in hardware, software, ora combination thereof. The order in which the process is described isnot intended to be construed as a limitation, and any number of thedescribed blocks may be combined in any order to implement the process,or an alternate process.

FIG. 6 illustrates a flow diagram representation of a method to retaindata in a storage device in a stand-by mode. The supply voltage as wellas the Rail to Rail (RTR) voltage at the storage array nodes areconstantly monitored at blocks 601 and 602. The operating band of Railto Rail (RTR) voltage is then determined (blocks 603, 604) by checkingthe RTR voltage against the set supply voltages such as V1, V2 and V3described in embodiment illustrated by FIG. 1. Therefore, it is firstverified, whether the RTR voltage lies between supply voltages V1 and V2at block 603, i.e., an operating band of low voltages. If Yes, then nosleep is applied to either header or footer at block 605; else, it isverified whether the RTR voltage lies between supply voltages V2 and V3at block 604, i.e., an operating band of intermediate voltages. If Yes,then either of the header or footer is configured to stand-by mode atblock 606; else, sleep is applied to both header and footer at block 607as the RTR voltage is then >supply voltage V3, which is an operatingband of high voltages. Therefore, on determining the operating band ofthe RTR voltage, the voltage provided at each storage array node isselectively altered.

FIG. 7 illustrates a graphical representation of generation of a controlsignals by the RTR voltage monitor in accordance with an embodiment ofthe present disclosure where the representation is plotted over voltageand time. As is clear from the representation, at around VDD=0.82V theRTR voltage monitor generates a control signal which applies full sleepto the memory core at higher supply voltages, i.e., the entire memorycore is configured to stand-by mode at a higher supply voltage VDD.Thus, the issue of noise margin at low voltages where stability is aconcern rather than leakage current is effectively dealt with.

FIG. 8 describes a graphical representation of leakage variation withrespect to current in accordance with an embodiment of the presentdisclosure. At low voltage supply available at the supply voltage nodes,only the footer control is implemented hence, there is less reduction inleakage. At around 0.82V, the header control is also triggered to beactive and leakage reduction is more. A critical leakage zone for thedevice is at higher voltages where full sleep is applied i.e., bothheader and footer are inactive.

Various embodiments of the present disclosure are applicable to allvolatile memories such as SRAM (Static Random Access Memory), DRAM(Dynamic Random Access Memory) as well as a few ROM architectures.

Embodiments of the present disclosure utilize less area where inspecific cases of implementation have resulted in a penalty less than0.2% of memory area as was being utilized previously. Further, specificcases have also resulted in a 100% increase in RNM (Retention NoiseMargin) at low voltages.

A memory with sleep circuitry as described above may be coupled toanother integrated circuit (IC), such as a processor or controller toform a system.

Furthermore, sleep circuitry such as described above may be used inother than memory circuits.

Although the disclosure of system and method has been described inconnection with the embodiment of the present disclosure illustrated inthe accompanying drawings, it is not limited thereto. It will beapparent to those skilled in the art that various substitutions,modifications and changes may be made thereto without departing from thescope and spirit of the disclosure.

The various embodiments described above can be combined to providefurther embodiments. Aspects of the embodiments may be modified, ifnecessary to employ concepts of the various patents, applications andpublications to provide yet further embodiments.

These and other changes may be made to the embodiments in light of theabove-detailed description. In general, in the following claims, theterms used should not be construed to limit the claims to the specificembodiments disclosed in the specification and the claims, but should beconstrued to include all possible embodiments along with the full scopeof equivalents to which such claims are entitled. Accordingly, theclaims are not limited by the disclosure.

From the foregoing it will be appreciated that, although specificembodiments have been described herein for purposes of illustration,various modifications may be made without deviating from the spirit andscope of the disclosure. Furthermore, where an alternative is disclosedfor a particular embodiment, this alternative may also apply to otherembodiments even if not specifically stated.

1. A storage device capable of retaining data in a stand-by mode, saidstorage device comprises: one or more storage array nodes; a Rail toRail voltage adjustor configured to selectively alter the voltageprovided at each said storage array node during the stand-by mode; astorage array operatively coupled to said Rail to Rail voltage adjustor;and a Rail to Rail voltage monitor operatively coupled to said storagearray nodes and configured to control said Rail to Rail voltage adjustorto provide sufficient voltage to retain data during the stand-by mode.2. A storage device as claimed in claim 1 wherein said storage arraycomprises an array of memory cell rows and columns operable in astand-by mode.
 3. A storage device as claimed in claim 1, wherein saidRail to Rail voltage adjustor comprises at least one switchedvoltage-reduction element.
 4. A storage device as claimed in claim 1wherein said Rail to Rail voltage monitor comprises a low leakagetracking block producing at least one control signal depending on thesupply voltage.
 5. A storage device as claimed in claim 4 wherein saidlow leakage tracking block comprises: a reference column comprising anarray of memory cell rows and columns greater than memory cell rows andcolumns in the storage array; and a level sensing block comprising noninverting buffer.
 6. A system capable of retaining data in a stand-bymode, said system comprises: one or more storage array nodes; a Rail toRail voltage adjustor configured to selectively alter the voltageprovided at each said storage array node during the stand-by mode; astorage array operatively coupled to said Rail to Rail voltage adjustor;and a Rail to Rail voltage monitor operatively coupled to said storagearray nodes and configured to control said Rail to Rail voltage adjustorto provide sufficient voltage to retain data during the stand-by mode.7. A system as claimed in claim 6 wherein said storage array comprisesan array of memory cell rows and columns operable in a stand-by mode. 8.A system as claimed in claim 6, wherein said Rail to Rail voltageadjustor comprises at least one switched voltage-reduction element.
 9. Asystem as claimed in claim 6 wherein said Rail to Rail voltage monitorcomprises a low leakage tracking block producing at least one controlsignal depending on the supply voltage nodes.
 10. A system as claimed inclaim 9 wherein said low leakage tracking block comprises: a referencecolumn comprising an array of memory cell rows and columns greater thanmemory cell rows and columns in the storage array; and a level sensingblock comprising non inverting buffer.
 11. A method for retention ofdata in a storage device during standby mode comprising: monitoring eachsupply voltage node operatively coupled to said storage array;monitoring Rail to Rail voltage at each storage array node of saidstorage array; determining an operating band of Rail to Rail voltage;and selectively altering voltage provided at each said storage arraynode during the stand-by mode.
 12. A method as claimed in claim 11wherein selectively altering the voltage provided at each storage arraynode comprises: applying no sleep to the storage device when the Rail toRail voltage falls within an operating band of low voltages; applyingsleep either to header or footer of the storage device when the Rail toRail voltage falls within an operating band of intermediate voltages;and applying full sleep to the storage device when the Rail to Railvoltage falls within an operating band of high voltages. 13-48.(canceled)